Limitations of ilp in computer architecture pdf

The performance of processors an ambitious level of hardware support equal to or better than what is likely in the next five years.

In particular we assume the following fixed attributes:. Up to 64 instruction issues per clock with no issue restrictions. As we discuss later, the practical implications of very wide issue widths on clock rate, logic complexity, and power may be the most important limitation on exploiting ILP. A tournament predictor with 1K entries and a entry return predictor. This predictor is fairly comparable to the best predictors in ; the predictor is not a primary bottleneck.

Register renaming with 64 additional integer and 64 additional FP registers,exceeding largest number available on any processor in 41 and 41 in the Alpha , but probably easily reachable within two or three years.

Developed by Therithal info, Chennai. Toggle navigation BrainKart. Posted On : The Hardware Model 2. Limitations of ILP 1. The assumptions made for an ideal or perfect processor are as follows: 1. Memory-address alias analysis—All memory addresses are known exactly and a load can be moved before a store provided that the addresses are not identical.

Limitations on the Window Size and Maximum Issue Count A dynamic processor might be able to more closely match the amount of parallelism uncovered by our ideal processor. The Effects of Realistic Branch and Jump Prediction: Our ideal processor assumes that branches can be perfectly predicted: The outcome of any branch in the program is known before the first instruction is executed. The five levels of branch prediction shown in these figures are 1. Limitations on ILP for Realizable Processors The performance of processors an ambitious level of hardware support equal to or better than what is likely in the next five years.

In particular we assume the following fixed attributes: 1. The Hardware Model. An ideal processor is one where all constraints on ILP are removed. The only limits on ILP in such a processor are those imposed by the actual data flows through either registers or memory.

The assumptions made for an ideal or perfect processor are as follows:. Register renaming. Branch prediction. All conditional branches are predicted exactly. Jump prediction. When combined with perfect branch prediction, this is equivalent to having a processor with perfect speculation and an unbounded buffer of instructions available for execution.

Memory address alias analysis. Note that this implements perfect address alias analysis. Perfect caches. In practice, superscalar processors will typically consume large amounts of ILP hiding cache misses, making these results highly optimistic.

To measure the available parallelism, a set of programs was compiled and optimized with the standard MIPS optimizing compilers. The programs were instrumented and executed to produce a trace of the instruction and data references.

Every instruction in the trace is then scheduled as early as possible, limited only by the data dependences. Since a trace is used, perfect branch prediction and perfect alias analysis are easy to do. With these mechanisms, instructions may be.

So there will be 4 functional units, each attached to one of the operations, branch unit, and common register file in the ILP execution hardware. Let the respective latencies be 1, 2, 3, 2, 1. Let the sequence of instructions be —. Skip to content. Change Language. Related Articles. Table of Contents. Improve Article.